1. Technical Field
The present invention relates to error detection and correction in memory storage systems and more particularly to efficient systems and methods for error detection and correction using statistical methods in high density storage systems.
2. Description of the Related Art
Typical semiconductor computer memories are fabricated on semiconductor substrates consisting of arrays of a large number of physical memory cells. In general, one bit of binary data is represented as a variation of a physical parameter associated with a memory cell. Commonly used physical parameters include threshold voltage variations of Metal Oxide Field Effect Transistors (MOSFET) due to the amount of charge stored in a floating gate or a trap layer in non-volatile Electrically Erasable Programmable Read Only Memory (EEPROM), resistance variation of the Phase Change memory element in Phase-change Random Access Memory (PRAM) or Ovonic Unified Memory (OUM), charge storage variation of the capacitor in volatile Dynamic Random Access Memory (DRAM) and reflectivity variation of Phase Change material on a Compact Disc Read Only Memory (CDROM).
Costs of memory storage systems are strictly dependent on the amount of information that can be stored in a given area of a semiconductor substrate or storage media. Aside from minimizing the area of each physical memory cell by decreasing the critical dimension of the manufacturing process, one cost effective technique to increase the information storage in a memory storage system is to increase the amount of information that can be stored in each physical memory cell in the storage system.
Increasing the number of bits to be stored in a single physical memory cell is an effective method for lowering manufacturing costs per bit. Multiple bits of data can be stored in a single memory cell when variations of the physical parameter can be associated with multiple bit values. This multiple bit storage memory cell is known as a Multi-Level Cell (MLC). A significant amount of effort in memory device and circuit designs is devoted to maximize the number of bits to be stored in a single physical memory cell. This is particularly true with storage class memory such as popular non-volatile Flash memories commonly used as mass storage devices.
The basic requirement for multiple bit storage in a memory cell is to have the spectrum of the physical parameter variation to accommodate multiple non-overlapping bands of values. The number of bands required for an n-bit cell, for example, is 2n. A 2-bit cell needs 4 bands, a 3-bit cell needs 8 bands and so forth. Thus, the available spectrum of a physical parameter in a memory cell is the limiting factor for multiple bit memory storage.
In addition to limiting spectrum width, fluctuations in environmental variables such as temperature, power and time affect all operations and data integrity of a typical storage device. Data integrity is a major problem for data storage systems due to the fluctuations in environmental variables. It is desirable to devise a cost effective method to preserve the integrity of the stored data in semiconductor storage systems.
Referring to FIG. 1, a storage system 10 is subject to variations in environment 22 such as temperature, power and storage time which may cause variations and decay in the values data 12 through memory processes such as programming 14, storage 16 and reading 18 thus further limiting the information storage of retrieved data 20.
Data 12 to be stored is acquired. The data 12 may come from various sources, such as a Central Processing Unit (CPU) or a peripheral device coupled to a memory unit with the memory cell. The programming operation 14 writes acquired data 12 into the memory cell. Depending on the storage technology used, writing data may include storing charge in a capacitor for charge storage, applying voltage to the source, drain, or control gate in a floating gate transistor for threshold voltage variation, etc. After the data is written into memory, it is stored for a period of time at storing operation 16. At some time in the future, the data is retrieved from the memory cell during a reading operation 18. The data is finally retrieved at operation 20.
As illustrated, the environment 22 (both internal and external to the memory cell) affects the programming 14, storage 16, and reading 18 of the data. Environmental factors such as, but not limited to, humidity, time, temperature, magnetic fields, and electrical fields may cause charge leakage or change resistance levels in memory. More generally, the characteristic parameter used to delineate binary values in the memory cell may shift over time due to environmental conditions. The environmental factors 22 cause data distortion so that the data 20 extracted from the memory cell may not be the same as the data 12 input to the memory cell.
While defective bits which are usually caused by imperfections in manufacturing can generally be identified by reliability test procedures and be replaced with redundant bits in high density memory, normal statistical fluctuations of the physical parameter will result in natural dispersion of the values of the physical parameter which cannot be identified with test procedures. To guard against this intrinsic dispersion of the physical parameter values, wide bands of the parameter values are used in the prior art to represent each binary bit to be stored in the memory cells to assure data integrity. This band structure used in the prior art is illustrated in FIG. 2A and FIG. 2B.
Referring to FIG. 2A, a number of memory cells (y-axis) versus parameter values (P) (x-axis) for data stored is plotted to provide probability distributions. The probability distributions in FIG. 2A show wide bands of the parameter values used to represent binary information stored in the memory cells to assure data integrity. FIG. 2A includes bands from Pmin to Pref1, Pref1 to Pref2, Pref2 to Pref3 and Pref3 to Pmax.
Referring to FIG. 2B, the parameter values are subject to dispersion as illustratively shown. To guard against this dispersion of the parameter values, the bands are made wide enough to retain dispersed distributions within the respective bands assuring data integrity as depicted in FIG. 2B. As illustrated in FIG. 2A and FIG. 2B, the prior art is not using the available bandwidth efficiently. In order to accommodate the natural statistical dispersions of the memory cell distributions within the respective bands of the characteristic parameter, the bands are designed to be relatively wide with respect to the dispersions. Therefore auxiliary systems and methods are needed to increase the information capacity of a storage device with memory cells of a given characteristic parameter bandwidth.